| 摘要 |
A computer input-output bus system employing an analog module-presence line by which a controller can detect if no modules, one module or more than one module have been selected in the addressing phase of each operation. Each module generates a unique code related to its position in the structure of the bus and returns it to the controller, so that other errors in selection are detected. In case of a detected error, write commands are terminated prematurely by the controller before being acted on by any incorrectly-selected module. Timings of signals on the bus are fixed with respect to a constant-frequency clock signal, as illustrated in Figure 1. <IMAGE> |
