| 摘要 |
PCT No. PCT/FR96/00469 Sec. 371 Date Feb. 19, 1997 Sec. 102(e) Date Feb. 19, 1997 PCT Filed Mar. 28, 1995 PCT Pub. No. WO96/31006 PCT Pub. Date Oct. 3, 1996An ECL level/CMOS level logic signal interfacing device includes, connected in cascade, a circuit for generating an in-phase relationship with an ECL level input signal, a threshold inverter circuit receiving the in-phase signal at an inverter input and delivering an inverted in-phase signal, a shaping inverter circuit receiving the inverted in-phase signal and outputting a calibrated in-phase signal, and an output amplifier circuit receiving the calibrated in-phase signal and outputting an output signal to the CMOS level in phase relationship with the ECL level input signal. The circuits are supplied with a CMOS level supply voltage relative to a reference voltage.
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