发明名称 |
Floating point multiplier with reduced critical paths using delay matching techniques |
摘要 |
A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors to generate the 53x53 double-precision product. Delay matching techniques in the binary tree stage and in the final addition stage reduce cycle time. Improved rounding and sticky-bit generating techniques further reduce area and timing. The overall multiplier has a latency of 3 cycles, a throughput of 1 cycle, and a cycle time of 6.0 ns.
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申请公布号 |
US5790446(A) |
申请公布日期 |
1998.08.04 |
申请号 |
US19950498145 |
申请日期 |
1995.07.05 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
YU, ROBERT K.;ZYNER, GREGORY B. |
分类号 |
G06F7/487;G06F7/506;G06F7/52;G06F7/53;G06F7/533;(IPC1-7):G06F7/52;G06F7/44 |
主分类号 |
G06F7/487 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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