发明名称 System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer
摘要 A multiprocessor computer system and method for maintaining coherency between virtual-to-physical memory translations of multiple requestors in the system. A poison bit is associated with a memory block in the system. The poison bit is set to indicate that a virtual-to-physical memory translation for the memory block is stale. An exception is generated in response to an access by one of the requestors to the memory block if the poison bit is set, thereby indicating to the requestor that the virtual-to-physical memory translation entry for the memory block is stale. The virtual-to-physical memory translation for the memory block is then updated with a virtual memory translation corresponding to a new physical location for the memory block. In an embodiment having a cache-based multiprocessor system, the method further comprises the step of invalidating all cached copies of the memory block. In this case, the invalidating step and the setting step must be performed as an atomic operation.
申请公布号 US5787476(A) 申请公布日期 1998.07.28
申请号 US19950435459 申请日期 1995.05.05
申请人 SILICON GRAPHICS, INC. 发明人 LAUDON, JAMES P.;LENOSKI, DANIEL E.
分类号 G06F12/08;G06F12/10;(IPC1-7):G06F12/00 主分类号 G06F12/08
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