发明名称 Power saving PLL circuit
摘要 A phase lock loop includes a voltage controlled oscillator (VCO), a phase comparator for comparing the phases of the output of the VCO and a reference signal, a charge pump circuit, including a plurality of current sources, for supplying a control voltage by charging or discharging a capacitor based on the outputs of the current sources, and a current source controller for controlling the current output of the current sources by a n-bit current control signal. Charge current and discharge current by the charge pump circuit are controlled in n bits so that a rapid synchronization during lock-in and a low jitter after lock-in can be obtained.
申请公布号 US5783972(A) 申请公布日期 1998.07.21
申请号 US19960757806 申请日期 1996.11.27
申请人 NEC CORPORATION 发明人 NISHIKAWA, MASATO
分类号 H03L7/093;H03L7/089;H03L7/095;H03L7/107;(IPC1-7):H03L7/089;H03L7/18 主分类号 H03L7/093
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