发明名称 |
Layout method for semiconductor memory device obtaining high bandwidth and signal line |
摘要 |
A semiconductor memory device architecture and method thereof obtains a high data bandwidth by forming multiple input/output lines. A unit array has a plurality of reference blocks formed in a length direction of the device, each reference block storing a plurality of memory cells. A sub array has a plurality of unit arrays formed in a longitudinal direction perpendicular to the length direction. A word line selects memory cells from within the reference blocks, the word line extending in the length direction. A pair of bit lines and a pair of data input/output lines extend in the longitudinal direction. The pair of data input/output lines are correspondingly connected to 2n (n=1,2, . . . ) pairs of bit lines. A read select signal line selects a pair of bit lines from among 2n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a read operation. A write select signal line selects a pair of bit lines from among 2n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a write operation. A column gate connects the pair of bit lines to the pair of data input/output lines. A column select line extends in the longitudinal direction and controls the column gate, and a pair of main data input/output lines are connected correspondingly through a multiplexer to a plurality of data input/output lines.
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申请公布号 |
US5783480(A) |
申请公布日期 |
1998.07.21 |
申请号 |
US19950580595 |
申请日期 |
1995.12.29 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
SEO, DONG-IL;JEONG, SE-JIN |
分类号 |
G11C11/401;G11C7/10;G11C11/407;G11C11/409;G11C11/41;H01L21/8242;H01L27/108;(IPC1-7):H01L23/528 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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