发明名称 Single-chip memory system having a multiple bit line structure for outputting a plurality of data simultaneously
摘要 To make a memory system smaller, a memory system includes a plurality of memory cell arrays including a plurality of pairs of bit lines, a plurality of first data amplifiers for amplifying data of corresponding pairs of bit lines, a reference voltage circuit for outputting a reference voltage level, and a plurality of second amplifiers for receiving an output of the corresponding first data amplifier and the reference voltage level, for judging which voltage level is higher between the output of the corresponding first data amplifier and the reference voltage level, and for amplifying the voltage level being higher.
申请公布号 US5784324(A) 申请公布日期 1998.07.21
申请号 US19970806667 申请日期 1997.02.26
申请人 NEC CORPORATION 发明人 OKAMURA, YOSHIFUMI
分类号 G11C11/41;G11C7/06;G11C7/10;G11C11/409;(IPC1-7):G11C7/00 主分类号 G11C11/41
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