发明名称 Parallel process scheduling method in a parallel computer and a processing apparatus for a parallel computer
摘要 A method and a processing apparatus for use in a parallel computer realizing a coordinate scheduling which does not degrade a throughput performance of a system. According to this invention, if a parallel process in execution gets into a parallel synchronization waiting state, the parallel process is deactivated so that allocation of the parallel process is inhibited, a process of another executable job is allocated, instead. If a setting condition is satisfied during the execution of another job, an interruption signal for a process in execution is generated to activate the parallel process in the parallel synchronization waiting state, thereby resuming allocation of this parallel process. This invention may be applied to a parallel computer system of a distributed main storage MIMD type which implements plural tasks in parallel by plural PEs.
申请公布号 US5781775(A) 申请公布日期 1998.07.14
申请号 US19960677984 申请日期 1996.07.10
申请人 FUJITSU LTD. 发明人 UENO, HARUHIKO
分类号 G06F15/173;G06F9/45;G06F9/46;G06F9/52;(IPC1-7):G06F9/00 主分类号 G06F15/173
代理机构 代理人
主权项
地址