CLOCK SUPPLY SYSTEM FOR BUS CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a clock supply system for suppressing the deterioration of a set-up/hold margin on the receiving side due to the propagation delay of a signal on a bus which appears especially when the operation frequency of a bus circuit is accelerated. SOLUTION: The bus circuit for transmitting/receiving a digital signal is provided with a clock bus 8 having almost the same route as a data bus 2 and a device for outputting a data signal to the data bus 2 simultaneously outputs a clock signal also to the clock bus 8, so that the same delay as the data signal is generated also in the clock signal and these signals are transmitted to each device on the receiving side.