发明名称 |
Programmable high performance mode for multi-way associative cache/memory designs |
摘要 |
The present invention provides circuitry which facilitates user selection of alternative memory accessing techniques. The present invention provides a design approach or technique to transform the time associated with waiting for a valid "way-select" signal into cycle reduction time, thus providing a beneficial increase in the overall performance of multi-way associative cache and memory designs.
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申请公布号 |
US5778428(A) |
申请公布日期 |
1998.07.07 |
申请号 |
US19950577167 |
申请日期 |
1995.12.22 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BATSON, KEVIN A.;ROSS, JR., ROBERT A. |
分类号 |
G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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