| 摘要 |
The circuit arrangement and method is for measuring a difference in capacitance between a first capacitance (C1) and a second capacitance (C2). A hitherto necessary compensation of a plurality of parasitic effects has become unnecessary due to isolated measurement of an unwanted capacitance (CP) with which parasitic effects, to which the first capacitance (C1) and the second capacitance (C2) are subject, are modelled. When an evaluation logic (AL) realized in digital form is employed, only one counter unit wherein a binary value proportional to the respectively measured capacitance is counted need be provided. By cyclical measurement of the unwanted capacitance (CP), the first capacitance (C1), the second capacitance (C2) and, at the end, the unwanted capacitance (CP) are determined. The unwanted capacitance (CP) is compensated when the counter unit respectively counts backward when "counting" the unwanted capacitance (CP) but otherwise counts forward. Each sub-cycle (T1,T2,T3,T4) lasts exactly N clocks, whereby the clocks are supplied by a measuring oscillator (MO). The clocks are dependent on the capacitance respectively measured.
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