| 摘要 |
A mechanism for adjusting the frame clock used by an audio DSP or other functional unit to transfer data to the rate at which data is transferred across an isochronous bus. According to one embodiment of the present invention, there is provided a mechanism for monitoring the level of data in a data buffer. The data are transferred to the buffer from the audio DSP, and then out the buffer across the isochronous bus, such as a Universal Serial bus. If the level in the buffer is too high, the audio DSP is filling the data buffer too quickly. If the data level in the buffer is too low, then the audio DSP is not providing the data quickly enough. The frame clock on the audio logic which is used to generate and transfer the data to the buffer is adjusted. Thus, if the level in the buffer is too high, the frame clock will be slowed; if the level in the buffer is too low, the rate of the frame clock will be increased. More particularly, there is provided a programmable clock divider which receives as input a master clock used by the audio DSP for computational purposes, and from which the frame clock is derived. Responsive to the level of data in the buffer, the programmable clock divider will adjust the rate of the frame clock.
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