| 摘要 |
PROBLEM TO BE SOLVED: To obtain precise synchronizing removal by small circuit constitution or processing by successively adding a product sum data group successively obtained between with an inverse spread code group concerning over sampling data by a product sum arithmetic means at a prestage by an adding arithmetic means at a poststage. SOLUTION: SR1 to SR8 are shift registers on each m(8) stage. Then, SR1 to SR8 time-sequentially store (delay) n×m (8×8) number of each revere spread data over-sampled by the 1/8 chip frequency of input. A product sum circuit consisting of residual constitution successively obtains product sums (correlated output) between n(8) number of each reverse spread data of every m(8) number of SR1 to SR8 and a reverse spread code C. In an arithmetic circuit 2 on a poststage, RG1 to RG8 time-sequentially store m-number of product sum data Σ1 with the timing of each 1/8 chip period of input. Each remaining adder circuit adds each product sum data RG1 to RG8 to obtain correlated data Σ2. |
