| 摘要 |
The computer arrangement includes a processor (P) which comprises a limited instruction set, and a memory (SP) which is coupled with the processor. A programmable logic block (PLA) is provided, with which at least one further instruction is implemented, which is not contained in the instruction set of the processor. The processor is pref. a digital signal processor (DSP), and the programmable logic block is a field-programmable gate-array (FPGA) or an Application-Specific IC. The programmable logic block is pref. formed in such way, that an interval encapsulation is accomplished, whereby the intervals are pref. scaled logarithmically. |
