| 摘要 |
A circuit arrangement for selectively connecting at least two inputs to a counting stage equipped with at least one preparatory input and one triggering input, wherein these inputs are connected in circuit with the triggering input of the counting stage through the agency of associated gates and a successively arranged common gate. A respective input of each associated gate is connected to a voltage via a respective switch controlling such gate. For the purpose of slowing down or retarding the switching-in signal flank there is connected in series with each switch an inductance coil and a damping resistor which collectively form in conjunction with a respective grounded capacitor an at least approximately critically damped series oscillating circuit. The junction point between each damping resistor and associated capacitor is connected via a diode and a common resistor to an oppositely poled voltage, and the junction point between each such diode and the common resistor is connected with the preparatory input of the counting stage. |
