| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a high-fineness display panel without increasing production stages while preventing the degradation in an aperture ratio by applying the potential of the adjacent gate line adjacent to the gate line of an upper electrode, i.e., the scanning line of a fore stage of post stage on the upper electrode. SOLUTION: The potential of the adjacent gate line adjacent to the gate line of the upper electrode 105, i.e., the scanning line of the fore stage or the post stage is applied on the upper electrode. Since charge storage capacitance having a lower electrode 18 is formed with the panel, charge storage may be executed by applying the arbitrary potential on the upper electrode 105 with respect to a drain electrode applied on the lower electrode 18. The selection period when a pulse signal is introduced to the gate potential in the image region to which the charge storage capacitance belongs is a non-selection region to the adjacent image region and the reference potential is applied on the adjacent gate line. The charges are stored between the upper electrode 105 and the lower electrode 18 by applying the potential of the adjacent gate line on the upper electrode 105, by which the holding performance of the voltage impressed on liquid crystals during the non-selection period of the image region is improved.</p> |
