发明名称 Optimizing method for logic circuit and logic circuit optimizing system
摘要 A logic circuit partitioning system includes a logic circuit network generating portion for inputting a logical expression group and generating a logic circuit network, in which each node corresponds to each logical expression and each branch corresponds to a relationship between each logical expression, a matrix generating portion inputting the generated logical circuit network and generating a matrix, in which each row corresponds to the node in the logical circuit network and each column corresponds to an input of the logical circuit and node, and an arbitrary value is given for each element in the column corresponding to the input for the node corresponding to each row, a matrix partitioning portion for inputting the generated matrix and extracting a partial matrix which has sized in row and column greater than or equal to two and the arbitrary value at every elements therein from the matrix from the matrix generating portion, and a logic circuit network partitioning portion for partitioning partial circuit corresponding to the partial matrix extracted from the matrix, from the logic circuit network.
申请公布号 US5764527(A) 申请公布日期 1998.06.09
申请号 US19950549548 申请日期 1995.10.27
申请人 NEC CORPORATION 发明人 NAKAMURA, YUICHI
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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