发明名称 Synchronization arrangement for decoder/de-interleaver
摘要 A decoder de-interleaver comprises a de-interleaver for de-interleaving received interleaved encoded data that includes periodic decoder synchronization signals to produce de-interleaved encoded data. A decoder decodes the de-interleaved encoded data to produce output data. The de-interleaver has a latency such that the de-interleaved encoded data is delayed by (B-1) times a period of the decoder synchronization signals plus a constant interval, where B is the interleave depth. A synchronization pulse generator receives the interleaved and encoded data and generates decoder synchronization pulses that are substantially coincident with the decoder synchronization signals. A delay unit is connected between the synchronization pulse generator and the decoder for delaying the decoder synchronization pulses by the constant interval. The decoder thereby receives decoder synchronization pulses that correspond to previous decoder synchronization signals, but functions properly because the relative timing is correct. The decoder has an error detecting function by which the first B-1 decoder synchronization pulses that are generated before the de-interleaver produces valid de-interleaved encoded data are ignored.
申请公布号 US5761249(A) 申请公布日期 1998.06.02
申请号 US19960619300 申请日期 1996.03.21
申请人 LSI LOGIC CORPORATION 发明人 BEN-EFRAIM, NADAV
分类号 H03M13/00;H03M13/27;H03M13/33;H04L7/04;(IPC1-7):H04L27/06;H04L7/00 主分类号 H03M13/00
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