发明名称 FREQUENCY STABILIZING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent a voltage controlled oscillator from being controlled to oscillate an erroneous frequency due to reduction in a reception electric field strength by storing frequency difference information between an intermediate frequency signal and a frequency of a comparison signal from a reference oscillator as just preceding frequency in formation when an amplitude of the intermediate frequency signal is reduced more than a specified amplitude. SOLUTION: A level measurement device 4 always measures an amplitude of an intermediate frequency signal S2 denoting a reception electric field level and converts the measured amplitude into a DC voltage S5 and inputs the voltage to a comparator 5. The comparator 5 compares the DC voltage S5 with a reference voltage S4 from a reference power supply 14 to provide an output of a low gate control level S6 to gates 6, 8 so as to shut an amplified intermediate frequency signal S3 to be given to a frequency comparator section 10 and a comparison signal S8 from a reference oscillator 7 when the DC voltage S5 is lower than the reference voltage S4. Thus, while the reception electric field level is low, the oscillated frequency from a voltage controlled oscillator 13 is not fluctuated and the oscillated frequency is prevented from converging to an erroneous frequency.
申请公布号 JPH10150378(A) 申请公布日期 1998.06.02
申请号 JP19960318521 申请日期 1996.11.15
申请人 SAITAMA NIPPON DENKI KK 发明人 NOBUSAWA HIDEAKI
分类号 G01R23/15;H03J7/06;H03L7/14;H04B1/26 主分类号 G01R23/15
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