| 摘要 |
The sum of capacitance is determined by an LSI load characteristic extraction program 217, as for the capacitance of a plurality of wiring patterns constituting different segments of a wiring, between the wiring and a plurality of other wiring patterns adjacent to the wiring, and the resistance of each wiring pattern also is determined. On the basis of the resistance and capacitance, a load characteristic value 222 comprised of a plurality of predetermined lower order coefficients of series expansion of complex admittance at the driving point of that wiring is calculated. A delay calculation program 223 calculates delay time and power dissipation as the driving characteristic of logic gates which drive this wiring, according to the coefficients and a device characteristic library 212. The library 212 is generated in advance by a program 600, in which a plurality or lower order coefficients of series expansion obtained by series expanding the complex admittance of a plurality of wirings of different length, the delay time and power dissipation of a device when driving these wirings by that device are maintained. For evaluating the capacitance of respective wiring patterns, by dividing the substrate into a plurality of regions, using a region management table for registering a plurality of wiring patterns for each region, and detecting wiring patterns in the same region, the capacitance therebetween is calculated.
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