| 摘要 |
Each memory cell of an SRAM has a structure in which a gate electrode of a drive MOSFET is formed by a first conductive film, a gate electrode of a load TFT is formed by a third conducive layer and a second conductive film does not exist in an area where two gate electrodes overlap with each other. After the second conductive film is subjected to patterning, a first interlayer insulating film is successively removed with the same photolithographic mask. Since the parasitic capacitance at a memory node of the memory cell is increased by thinning the insulating film between the two gate electrodes, the SRAM has an excellent resistance to soft errors.
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