| 摘要 |
PROBLEM TO BE SOLVED: To secure a sufficient alignment margin and, at the same time, to reduce the level difference between a cell array area and a peripheral circuit area as much as possible, by forming landing pad contact holes through an interlayer insulating film, and filling up the contact holes with a conductive material for forming landing pads. SOLUTION: After gate electrodes 105 are formed on a substrate 101 and coated with spacers 107, and an oxide film is formed on the exposed surface of the substrate 101 between the gate electrodes 105, an etching stopping layer 109 is formed to such a thickness that the layer 109 does not fill up the spaces between the electrodes 105. Then, an interlayer insulating film 114 is formed on the substrate 101 and landing pad contact holes 116 are formed by patterning the insulating film 114 for exposing the spacers 107 and the etching stopping layer 109. Thereafter, landing pads 117a and 117b are formed by filling up the contact holes 116 with a conductive material after the surface of the substrate 101 is exposed by removing the etching stopping layer 109 and the oxide film. |
