| 摘要 |
PROBLEM TO BE SOLVED: To provide a three phase clock pulse generating circuit which performs a side panel display on 16:9 wide display element with a simplified peripheral circuit structure. SOLUTION: The output of 1/2 frequency dividing circuit 53 of source oscillation is provided with delay circuits 55 and 56, and the output of 1/4 frequency dividing circuit 54 of source oscillation is provided with delay circuits 57 and 58. A side panel mode screen and a full mode screen are driven by changing such switching of switches as to be appropriate timing between the times of the side panel mode and the full mode with a 1/3 frequency dividing reference signalϕ1 and the outputs of the circuits 53 and 54 being CPH1 through a switch 59 which switches them, a 1/3 frequency division delay signalϕ2 and the signals of the circuits 55 and 57 being CPH2 through a switch 60 which switches them, and a 1/3 frequency division delay signalϕ3 and the signals of the circuits 56 and 58 being CPH3 through a switch 61 which switches them.
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