DEFECT ANALYSIS MEMORY FOR MEMORY TESTER

摘要

A defect analysis memory for a memory tester comprising a fail data storage unit which has a fail data memory and a 1st memory control part and a mask data storage unit which has a mask data memory and a 2nd memory control part. The 1st memory control part generates a write enable signal to write fail data into an address corresponding to the fail data memory if the logic comparison result of the memory tester shows a defect in a test mode and reads the fail data from the fail data memory and supplies them to the mask data storage unit in a remove mode. The 2nd memory control part supplies mask data which are read from the mask data memory to the logic comparator of the memory tester as a prohibition signal to prohibit the logic comparison in the test mode and generates a write enable signal from the fail data which are read from the fail data memory and supplies the signal to the mask data memory to write the mask data into the corresponding address in the remove mode.