发明名称 HIGH TOLERANCE CAVITIES IN CHIP PACKAGES
摘要 The present invention is directed to a method for forming cavities in chip packages, by mounting the package in an inverted position, engaging a router bit with the package, and moving a router with the bit along a circumscribed area on the package in a counterclockwise direction, thereby reducing chip to package spacing, wire bond lengths and lowering inductance.
申请公布号 WO9820546(A1) 申请公布日期 1998.05.14
申请号 WO1997US19024 申请日期 1997.10.22
申请人 W.L. GORE & ASSOCIATES, INC. 发明人 PIPER, BOYDD
分类号 H01L21/48;H01L23/13 主分类号 H01L21/48
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