发明名称 |
System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache |
摘要 |
A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address of the instruction block's successor and information indicating the location of a branch instruction within the instruction block. Thus, the next cache block can be easily fetched without waiting on a decoder or execution unit to indicate the proper fetch action to be taken for correctly predicted branching.
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申请公布号 |
USRE35794(E) |
申请公布日期 |
1998.05.12 |
申请号 |
US19940285520 |
申请日期 |
1994.08.04 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
JOHNSON, WILLIAM M. |
分类号 |
G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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