Emitter coupled logic (ECL) gate which generates intermediate signals of four different voltages

摘要

A fully differential, low voltage ECL gate (300) receives differential input signals (A, Ax, B, Bx) and provides them to first and second differential amplifiers (306, 328). The first differential amplifier (306) amplifies and level shifts the differential input (A, Ax) to provide a differential output (OUTx). The second differential amplifier amplifies the second differential input (B, Bx) to provide an amplified output, OUT. The amplified output signal, OUT, provides a different voltage level than that provided by amplified level shifted output signal, OUTx. The amplified level shifted output (OUTx) of the first differential amplifier (306) is then compared to the amplified output (OUT) of the second differential amplifier (328) to provide either an AND gate or an OR gate function.