MEMORY REDUNDANCY CIRCUIT USING SINGLE POLYSILICON FLOATING GATE TRANSISTORS AS REDUNDANCY ELEMENTS

摘要

A read-only memory device (10) is provided which comprises an array of read-only memory cells arranged in rows and columns. An additional row (15) of flat, single polysilicon floating gate memory cells is provided. A row decoder (11) coupled to the array of read-only memory cells is responsive to addresses corresponding to rows in the array for selecting addressed rows. Control circuitry (18) including a programmable store for identifying a defective row in the array to be replaced by the additional row, selects the additional row and replaces the defective row in response to an address corresponding to the defective row. In addition, circuitry (19) is provided on the integrated circuit which allows access to the additional row of floating gate memory cells for programming the additional row. This structure is particularly applied to an array of mask ROM cells.