| 摘要 |
<p>A co-processor (Fig. 2) for performing modular multiplication comprising: means for receiving B and N binary data streams (bstr, nstr); means for receiving a data value A; adder means (Add1, Add2), subtractor means (Sub1, Sub2, Sub3) and multiplier means (Mul1, Mul2) coupled to sequentially process the B and N binary data streams and the data value A to produce a modulo-reduced multiplication value (A*B) mod N; wherein the means for receiving the binary data streams comprises: random access memory (B-RAM, S-RAM) for holding B and N values; and parallel-serial interface means for receiving parallel data from the random access memory and for producing therefrom the binary data streams B and N.</p> |
