发明名称 Data link module for time division multiplexing control systems
摘要 A programmable data link module is used on a time division multiplex data bus and includes a system master clock signal. The module is functional as an input device, an output device, or both as an input and output device. It receives data from the data bus during a selected time slot for a selected number of frames to control output devices connected to it. The data link module includes a clock loss signal for generating an inhibit signal when a loss of the master clock signal is detected. The inhibit signal will prevent any changes to the state of the output device during the duration of the loss of the master clock signal.
申请公布号 US5748616(A) 申请公布日期 1998.05.05
申请号 US19950565534 申请日期 1995.11.30
申请人 SQUARE D COMPANY 发明人 RILEY, ROBERT E.
分类号 G08C15/06;G05B19/042;G06F3/00;G08C15/12;H03K19/003;H03K19/0175;H04J3/00;H04J3/06;H04J3/14;H04L12/10;H04L12/40;H04L12/403;H04L25/02;H04L25/03;(IPC1-7):H04J3/00 主分类号 G08C15/06
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