| 摘要 |
<p>A dynamic memory (14) having a refresh control circuit (18) is comprised of a main array (15) of memory cells organized according to addresses. A first circuit (16, 41) is provided for performing external operations on addresses within the main array (15) of memory cells. A refresh data memory array (20) and a timing circuit (30) for producing timing information (32) related to the refresh rate of the cells of the main array (15) are provided. A write driver circuit (34) is responsive to a refresh signal (43) and a request for the performance of an external operation on a selected address in the main array (15) for writing a portion of the timing information (32) to the refresh data memory array (20) according to addresses corresponding to addresses used in the main array. A counter (36) generates a plurality of addresses and a second circuit (40), responsive to the generated addresses, reads the written portion of the timing information from the refresh data array (20). A logic circuit (42) is responsive to the portion of the timing information read from the refresh data array and the then current value of the timing information for producing the refresh signal (43) indicative of when a refresh is required. An arbitration circuit (48, 50, 56) selects either the refresh signal (43) or the request for the performance of an external operation. Select circuits (38, 39) are responsive to the arbitration circuit (48, 50, 56) for selectively conducting either the generated address or the selected address to row decoders (40, 41) within the first and second circuits to ensure that the main array (15) of memory cells and the refresh data memory array (20) are being operated upon at the same address. A method of intelligently refreshing a dynamic memory is also enclosed.</p> |
