| 摘要 |
PURPOSE:To reset simultaneously both an emulation CPU and a prototype system even under a break state by outputting a control reset signal with which an emulator controls the emulation CPU, to the prototype system through the logical gate circuit of an open collector type. CONSTITUTION:An input signal fed from a terminal (b) is always kept at a logic 1 while an emulator is kept under a break state. Therefore L is always kept at logic 1. Under such conditions, a signal which sets a control reset signal controlled by the emulator itself at an active low level is supplied to a terminal (c). Thus L2 is set at an active low level through an AND circuit G2, and an emulation CPUM is reset. While a prototype system is also reset since the signal of the terminal (c) is supplied to said system through a buffer circuit B1 of an open collector type. Thus the prototype system is reset simultaneously with M. |
