NONVOLATILE MEMORY CELL-ARRAY STRUCTURE AND ITS DRIVING METHOD

摘要

PROBLEM TO BE SOLVED: To provide a nonvolatile memory cell-array structure appropriate for multi-bit storage. SOLUTION: The cell array structure comprises a first string having a memory cell MC serially connected between a first first selection transistor ST1 and first second selection transistors ST2a and ST2b, and a second string having a memory cell serially connected between second first selection transistors ST1a, ST1b, and a second first selection transistor ST2. The first first selection transistors ST1 is connected to bit lines 90 and 99, and the first second selection transistors ST2a and ST2b are connected to common source lines 100 and 109. The second first selection transistors ST2a and ST2b are connected to the bit lines and the second second selection transistor ST2 is connected to the common source lines. The first and second strings, in the same column, commonly have one bit line and one common source line, while having different bit lines and different common source line.