发明名称 PLL CIRCUIT
摘要 PURPOSE:To obtain a clock locked to an input digital signal easily and surely by applying frequency correction of a variable frequency oscillation circuit during the absence of a digital signal. CONSTITUTION:The circuit consists of a phase comparator circuit 1, a variable frequency oscillation circuit 2, a 1/N frequency divider circuit 3, a reference signal generating circuit 4, a frequency discrimination circuit 5, a switch 6, a low pass filter 7, a clock generating circuit 8 and a frequency control signal generating means 10 and an absence detection means 11 consists of the reference signal generating circuit 4 and the clock generating circuit 8. Then the absence period of the digital signal is represented by the absence detection means 11 and the frequency correction of the variable frequency oscillation circuit 2 is applied during this period. Thus, the stable clock in phase with the inputted digital signal is easily obtained.
申请公布号 JPH01307317(A) 申请公布日期 1989.12.12
申请号 JP19880139023 申请日期 1988.06.06
申请人 MITSUBISHI ELECTRIC CORP 发明人 MATSUI SHIGERU
分类号 G11B20/14;H03L7/14 主分类号 G11B20/14
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