发明名称 Capacitor manufacturing method for integrated circuit
摘要 The method involves forming a metal plug (48) of the length of two metal layers (20,53), and contacting them, is located in a dielectric (36), parallel to the chip plane between the two metal layers of preset shape. Preferably the metal plug is of V, Al or Cu. First a metal layer (20) is deposited over one dielectric (22), patterned, and etched and another dielectric deposited on it, smoothed, patterned, and etched to form an aperture. The latter is filled with metal to form the metal plug. Then the second metal layer is deposited, patterned and etched.
申请公布号 DE19737294(A1) 申请公布日期 1998.04.16
申请号 DE1997137294 申请日期 1997.08.27
申请人 NATIONAL SEMICONDUCTOR CORP., SANTA CLARA, CALIF., US 发明人 ZHAO, JI, SAN JOSE, CALIF., US;TENG, CHIH SIEH, SAN JOSE, CALIF., US
分类号 H01L21/02;H01L23/522;(IPC1-7):H01L21/762;H01L27/01;H01L21/768 主分类号 H01L21/02
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