| 发明名称 |
Parallel multiplication logic circuit |
| 摘要 |
A multiplication circuit having a Booth decoder, a partial product generator and a computation and formatting circuit. An incrementing device is combined with the computation circuit, enabling an anticipated incrementation if it is desired to obtain a rounded result.
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| 申请公布号 |
US5740095(A) |
申请公布日期 |
1998.04.14 |
| 申请号 |
US19950501675 |
申请日期 |
1995.07.12 |
| 申请人 |
SGS-THOMSON MICROELECTRONICS, S.A. |
发明人 |
PARANT, PHILIPPE |
| 分类号 |
G06F7/53;G06F7/507;G06F7/52;G06F7/533;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/53 |
| 代理机构 |
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