Apparatus and method for resetting a microprocessor in the event of improper program execution

摘要

A microprocessor arrangement includes a microprocessor that executes a program which includes a plurality of watchdog instructions which are located in respective different portions of the program and all of which should be executed during execution of the program. An address bus receives addresses generated during execution of the program. An address decoder is responsive to receipt of a watchdog instruction from the address bus to activate one of a number of output lines thereof. The watchdog instructions are different from one another whereby, if the microprocessor is operating correctly, the output lines will be activated in a predetermined sequence. A watchdog circuit is responsive to the output lines being activated in other than the predetermined sequence to reset the microprocessor via a reset input.