发明名称 BIT OPERATION PROCESSOR AND COMPUTER SYSTEM
摘要 PROBLEM TO BE SOLVED: To fast perform decimal to binary conversion by providing a decimal to binary converter with which an address calculating part converts decimal data into binary data. SOLUTION: A memory address calculating part 105 of a bit operation processor BPU (binary coded decimal) 10 has an operand register 105a and a decimal to binary converter 105b. After the converter 105b converts decimal data of BCD notation which is stored in the register 105a into binary data, the address of data RAM that shows the binary data is accessed by BP-D-ADR (data input signal) 703, and data which sent from the data RAM via BP-D-RDAT (address output signal) 704 is stored in the register 105a. After that, the data is sent to a bit operation executing part 107. Thereby, a user can handle the address of the data RAM in a decimal notation, and also, the control of a hardware can be simplified in comparison with a conventional computer system in which a decimal converter is connected through an I/O device.
申请公布号 JPH1097462(A) 申请公布日期 1998.04.14
申请号 JP19960249382 申请日期 1996.09.20
申请人 HITACHI LTD 发明人 ARITA YUTAKA;NAKAMIGAWA TETSUAKI;KUROSAWA KENICHI;OKAMOTO TADASHI
分类号 G06F7/38;G06F7/493;G06F9/305;G06F12/02;G06F15/16;G06F15/177 主分类号 G06F7/38
代理机构 代理人
主权项
地址