OVERCHARGE/DISCHARGE VOLTAGE REGULATOR FOR EPROM MEMORY ARRAY

摘要

A method of high speed reading of data from an EPROM, in which a memory array (12) is programmed based on device status at intersections of rows and columns of the array to store data therein as 0's and 1's, uses a capacitive overcharging and discharging technique to enable fast voltage stabilization without drawing significant current. A row containing memory element (25) to be read is quickly overdriven to overcharge an effective capacitance associated with the row to substantially the maximum level of the EPROM supply voltage (Vdd) which may exceed the programmed threshold voltage of the selected memory element (25). The effective capacitance is thereupon discharged to voltage level below both the maximum level of the supply voltage (Vdd) and the programmed threshold. Then the status and data content of the selected memory element (25) are read by first grounding an electrode of a source-drain path of the transistor comprising the memory element (25) to cause current with substantially no DC component to flow through that path of the transistor. A sense amplifier (17) in source-drain path of the transistor is triggered to detect current flow therethrough as indicative of the data content of the memory element (25).