| 摘要 |
Disclosed is a clock synchronization device for a timing/frequency supplier which supplies a master clock to a CDMA base station. The clock synchronization device comprises a comparator(1), a front counter(2), a phase comparator(3), a loop filter(4), a crystal oscillator(5), a binary counter(6), a rear counter(7), a Phase Locked Loop(PLL) circuit, an offset generation portion(13), an offset adjustment portion(14), and a processor(15). The comparator compares a sine wave to ground and converts into TTL level and inputs to the counter and a control logic. The PLL circuit receives the output of the comparator and generates a clock. The offset generation portion reads an offset between an external IPPS and an internal IPPS and calculates a delta value for offset adjustment. The offset adjustment portion performs summing/subtraction function to synchronize with the clock. The processor controls the delta value. Thus, a synchronized clock is supplied to the external IPPS.
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