| 摘要 |
A dual back bias supply circuit includes a bias section, a standby/active clamping section, a low level/high level back bias generating section, a select controlling section and a back bias selecting section. The dual back bias supply circuit supplies a high back bias voltage generated by the high level back bias generating section to a P well of a DRAM, to reduce leakage current in case of standby mode or when low power driving is required, and supplies a low back bias voltage generated by the low level back bias generating section in case of active mode, to increase signal transmission speed.
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