发明名称 TAB-Lötflächengeometrie für Halbleiterbauelemente
摘要 A semiconductor chip (16) has a shape of a quadrangle. Bumps (17A, 17B) are arranged in a staggered fashion along at least one side of the semiconductor chip, and include first bumps (17A) and second bumps (17B) arranged inside the first bumps (17A). If each of the first bumps (17A) has a maximum width Bw1 and each of the second bumps (17B) has a maximum width Bw2 in a direction parallel to at least one side of the semiconductor chip, Bw2 > Bw1. If each of the first bumps (17A) has a maximum length Bd1 and each of the second bumps (17B) has a maximum length Bd2 in a direction perpendicular to at least one side of the semiconductor chip, Bd1 > Bd2. <IMAGE>
申请公布号 DE69408657(D1) 申请公布日期 1998.04.02
申请号 DE1994608657 申请日期 1994.12.19
申请人 KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP 发明人 IKEBE, KIMIHIRO, C/O INTELLECTUAL PROPERTYDIV., MINATO-KU, TOKYO 105, JP
分类号 H01L21/60;H01L23/485;H01L23/495 主分类号 H01L21/60
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