| 摘要 |
An amorphous silicon thin film transistor (a-Si TFT) or other a-Si device is produced by depositing and lithographically patterning a layer of doped semiconductor material such as microcrystalline or polycrystalline silicon to produce a conductive lead. The semiconductor material is deposited over an insulating region and over an exposed part of an amorphous silicon layer. The insulating region has an edge that is over and approximately aligned with an edge of a gate region. The doped semiconductor layer therefore forms a junction to the amorphous silicon layer at the edge of the insulating region, approximately aligned with the edge of the gate region. Self-aligned lithographic patterning is performed in such a way that the conductive lead overlaps the insulating region by a distance that is no more than a maximum overlap distance. The maximum overlap distance can, for example, be no more than 1.0 mu m, and can be 0.5 mu m. The insulating region and the doped semiconductor layer can both be lithographically patterned by a combination of self-aligned backside exposure and top masked exposure. Overlap distance can be controlled by timing backside exposure, application of developer, baking, or application of etchant.
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