| 摘要 |
A clock frequency limiting circuit is disclosed. The clock frequency limiting circuit allows a semiconductor device to be fabricated, packaged and tested before the maximum clock frequency is set. The maximum clock frequency is set by burning a bank of on-chip fuses. The clock frequency limiting circuit counts clock cycles of an applied clock signal for a predetermined amount of time. A comparator compares the maximum clock frequency in the fuse bank and the counted clock cycles. A violation "kill" signal is asserted if the counted clock cycles exceeds the set maximum clock frequency. |
