| 摘要 |
PROBLEM TO BE SOLVED: To prevent the over-etching of the bottoms of connecting holes each of which has a small aspect ratio for connecting an upper and lower wirings, when these connecting holes and connecting holes for connecting the wirings and semiconductor elements are formed simultaneously. SOLUTION: A DRAM has information-storing capacitive elements C with a silicon oxide film 37 deposited on the tops of these elements. This film 37 is simultaneously etched to form connecting holes 38-42 into the tops of plate electrodes 34 and MISFETs (n- and p-channel MISFET Qns and Qps) of the peripheral circuit. To do this, plugs 29 are previously formed at the bottoms of the connecting holes 39-42 of the peripheral circuit to avoid causing large differences between the aspect ratios of the connecting holes 38 at the tops of the capacitive elements C and those of 39-42 at the tops of the MISFETs of the peripheral circuits. |
