Circuitry and methods for erasing EEPROM transistors

摘要

Circuitry and methods for performing a global erase of an array of electrically-erasable programmable read-only memory (EEPROM) transistors are provided. The voltages used to erase the EEPROM transistors are controlled so that the maximum voltage across the gate oxide of previously erased transistors in the array does not exceed a predetermined maximum acceptable voltage level, thereby avoiding gate oxide damage due to high electric fields.