| 摘要 |
PROBLEM TO BE SOLVED: To supply a clock capable of maintaining nonoverlap until a final stage latch, irrespective of a frequency in the shift register. SOLUTION: The register is equipped with a pair of nonoverlap clocks. One clock is propagated from an input 138 of the shift register to an output in the direction of a data flow, and the other clock is propagated from the output 140 to the input in the direction opposite to the data flow. This clocking is switched from the clock to propagate in the direction of the data flow to the clock to propagate in the direction opposite to the data flow in a point where both clocks become about the same delay from their generating sources. Consequently, after switching the clock propagating in the direction of the data flow over to the clock propagating in the direction opposite to the data flow, the clocking delay is gradually offset, and then the delay becomes zero at the final stage of the shift register. |
