发明名称 |
Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit |
摘要 |
A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.
|
申请公布号 |
US2007216462(A1) |
申请公布日期 |
2007.09.20 |
申请号 |
US20070798535 |
申请日期 |
2007.05.15 |
申请人 |
RENESAS TECHNOLOGY CORP. |
发明人 |
ISHIMI KOICHI |
分类号 |
G06F1/04;G06F1/10;G06F1/08;H03K5/04;H03K5/156;H03K7/08;H03K19/0175;H03L7/08;H03L7/099 |
主分类号 |
G06F1/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|