| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device which ensures latch up resistance and electrostatic breakdown resistance even with a substrate potential generator, without reducing its operation speed. SOLUTION: A device comprises a P-type substrate 10, a substrate potential generator 80 to apply an electric potential, a CMOS inner circuit 12, an electrostatic-breakdown prevention protection device 74 and a latch up prevention protecting device. The latch up prevention protecting device has an N-type first diffusion region 90 on the P-type substrate 10. In the first diffusion region 90, an N-type second diffusion region 92 connected to an input terminal, and a P-type third diffusion region 94 to which a power-source voltage Vcc is applied, are provided. The first diffusion region 90 is surrounded by an N-type fourth diffusion region 96 to which a ground voltage Vss is applied, in a flat pattern. |
