| 摘要 |
<p>PCT No. PCT/FR92/01073 Sec. 371 Date May 18, 1994 Sec. 102(e) Date May 18, 1994 PCT Filed Nov. 19, 1992 PCT Pub. No. WO93/10627 PCT Pub. Date May 27, 1993.A process for synchronizing a scanning circuit of a device for the display of images acquired by a camera having a scanning circuit controlled by a given acquisition clock. The device comprises an input buffer, a processor making it possible to reconstitute each image entering the buffer, a display store in which the images are recorded after processing and a controller able to control the reading or writing of the images in the display store. The process is characterized in that it consists of applying to the scanning circuit an arbitrary clock signal independent of the image synchronization of the signal received. Also, the reading and writing of the display store is controlled in order to obtain repetitions or suppressions of images on display thus absorbing any delay or advance. Further, the processor should have a faster than necessary image compression (average time of one image).</p> |
